1. Field of the Invention
The present invention relates to the field of semiconductor device fabrication, and more specifically to a methodology for laying out a device layer, a mask set produced by the layout, and a method of patterning a photosensitive layer.
2. Background Information
In the semiconductor industry, there is a continuing effort to increase device density by scaling device size. In order to form small dimensioned features, a variety of phase-shifting techniques have been proposed. In some of these methods, features are defined by forming open regions in an opaque layer on a mask or reticle (referred to generally as "mask" herein). The open regions transmit substantially all radiation incident thereon. Near or surrounding these open regions are phase-shifters which also transmit some or all of the radiation incident thereon, but which shift the phase of the radiation approximately 180.degree. relative to the openings forming the features. In this way, the radiation from the phase-shifter destructively interferes with the radiation from the feature, providing good contrast at the feature's edge.
A further method of using phase-shifting to form small features may be referred to as phase-edge phase-shifting. In this method, the destructive interference at the interface of two regions that transmit radiation approximately 180.degree. out of phase is used to form the feature. This method is illustrated in FIG. 1. Mask 100 comprises a first region 101, which may be referred to as the 0.degree. phase, and a second region 102, which may be referred to as the 180.degree. phase. As shown, the second region 102 is adjacent to the first region 101 along interface 105.
Intensity curve 110 shows the intensity of radiation at the image plane, I, as a fraction of the intensity incident on the mask 100,I.sub.O. As shown, the intensity 111 underneath region 101 away from the interface 105 is nearly equal to the intensity incident on region 101. Similarly, the intensity 112 underneath section 102 away from interface 105 is nearly equal to the intensity incident on region 102. However, underneath the interface 105 there is a sharp drop 115 in the intensity at the image plane due to the destructive interference between the radiation transmitted through regions 101 and 102. The exposure conditions can be adjusted such that the portion of the photosensitive layer underneath interface 105 is substantially unexposed, while portions of the photosensitive layer under regions 101 and 102 away from interface 105 are substantially exposed. In the case of a positive photoresist layer, after exposure and development, a thin line of photoresist will remain in the region underneath interface 105, while the remainder of the photoresist layer will be removed. In the case of a negative photoresist layer, after exposure and development, the unexposed region underneath interface 105 will be removed while photoresist under the remainder of the photosensitive layer will be hardened, and will remain after development. Thus, the phase-edge method may be used to form a narrow line in a positive photoresist layer, or a narrow opening in a negative photoresist layer.
One problem in implementing the phase-edge method is the difficulty in producing the device layer layout used to produce the masks used to define the device layer in the lithographic process. The phase-edge method typically requires at least two masks to implement. One mask, which may be referred to as the phase-edge mask, comprises phase-shifted regions to produce the small dimension lines described above. A second mask is used to eliminate unwanted lines produced from the phase-edge mask. The second mask may comprise device features defined by opaque and transparent regions on the mask. As will be described below, while there are known methods to produce a layout of the device features, there is no simple way to generate a layout of the phase-edge layer.
Referring to FIG. 2, a plan view of a portion of a device layer is shown. As can be seen, a plurality of features 201-205 are present. It will be appreciated that the features 201-205 are for illustration purposes, and the device layer may have many different features and/or the features may have different configurations, depending upon the device layer being formed. It will further be appreciated that there will typically be many more features in other regions of the device layer not shown.
To form the features of FIG. 2 using the phase-edge method, a mask such as that shown in FIG. 3 may be employed. As shown, the mask 300 comprises a plurality of 180.degree. regions and a plurality of 0.degree. regions. As described above, in the case of positive photoresist, a thin line will be formed at every interface.
Note that since the 0.degree. regions and the 180.degree. regions are two dimensional regions, it is not practical to form an isolated 0.degree./180.degree. interface. That is, an isolated line cannot be formed by a mask such as mask 300 of FIG. 3, but rather loops or closed polygon structures are formed. Thus, as mentioned above, a second exposure must be performed to remove unwanted portions of the phase-edge layer. For example, a photoresist layer may be exposed to mask 300 and to a mask having features 201-205, etc., prior to development. The exposure to mask 300 will produce very small dimension lines, and the exposure to the second mask will eliminate unwanted portions. For example, a latent image corresponding to the interface 301 will be formed in the photosensitive layer due to exposure to mask 300, while portions 301a of the latent image will be exposed and therefore eliminated after exposure to the second mask. Thus, in a positive photosensitive layer, a thin line corresponding to interface 301, without sections 301a, will remain.
Many techniques are known for generating a layout such as that shown in FIG. 2. Typically, circuit requirements, and various design rules, are input into a design system which then creates a layout. For example, as is well known, device layers are typically laid out with reference to points of a pre-defined grid. The grid points may be spaced at, for example, 0.1.mu.. Features are defined in relation to the grid, by placing all vertices at some grid point. For example, referring to FIG. 2, corner 250 of feature 201 may be defined at a certain grid point. If feature 201 is to have a width of 0.6.mu., corner 251 will be spaced six grid points to the right. Similarly, the other vertices points 252-255 will be placed at the appropriate grid points to give feature 201 the desired shape, width, and length. In placing features such as features 201-205, the program will take in to account the desired circuit, as well as various design rules. For example, features typically have minimum dimensions (for example, a design rule may be that a feature must be at least 0.6.mu.wide). In addition, the design rules include a minimum spacing requirement between any portion of the features. Also, the design rules typically specify a minimum pitch between features. For example, if the minimum pitch were 1.2.mu., then a portion of, for example, feature 203 such as edge 203a must be at least 1.2.mu.from edge 204a of feature 204. In addition, there may be other design rules dictated by device or process requirements that must be obeyed by the program in creating the layout.
As mentioned above, methods of automatically producing a design layer layout wherein desired circuits, and design rules, are specified and a corresponding design is then automatically produced are well known in the art. The design system typically may have one or more compaction routines which shrink or otherwise optimize the layout. Although a device layer comprising features such as those shown in FIG. 2 may be generated automatically, it is not an easy task to generate the layout for mask 300. This is because existing systems have no way to convert existing rules, using existing systems, into a layout of regions such as that shown in FIG. 3. Further, the existing systems have no way to convert a layout for features such as those shown in FIG. 2 into a layout for a reticle 300 of FIG. 3 using existing rules and design systems. While a small portion, such as that shown in FIG. 3 may be drawn by hand, such would be an extremely difficult task for an entire chip, as many devices contain millions of transistors, and devices in the future can be expected to contain tens of millions of transistors.
The phase-edge technique has also been proposed to form contacts in a negative resist. In one method, a negative photosensitive layer is exposed to a first reticle having strips of alternating 0.degree. and 180.degree. regions to form a first set of phase-edges. Then, the photosensitive layer is exposed to a second reticle also having strips of alternating 0.degree. and 180.degree. regions, to form a second set of phase-edges which are arranged substantially orthogonal to those of the first reticle. After these two exposures, a small dimension latent image is formed at every intersection of the first and second sets of phase-edges. Finally, a third exposure is performed using a standard contact mask to expose those latent images where no contact is desired, and mask those where a contact opening is desired. However, as described above in relation to FIG. 2, it is difficult to produce automatically a layout of the masks using known layout techniques.
It should also be noted that at least one further photolithographic technique, referred to herein as the single-edge feature method has the same layout problem as described above for the phase-edge technique. In this method, a layer of, for example, oxide may be deposited on a substrate. The layer is patterned using a mask similar to mask 300 of FIG. 3, except that one of the 0.degree. or 180.degree. regions are replaced with opaque regions, while the other of the 0.degree. and 180.degree. regions remain transmitting. If desired, enhancement techniques such as phase-shifting may be used. After development of, e.g., a positive photosensitive layer, and etching of the oxide, oxide regions corresponding to the opaque regions remain. For example, referring to FIG. 4A, an oxide region 402 on a substrate 401 is shown. Next, a layer 403, such as polysilicon, is deposited. Following deposition of layer 403, an anisotropic etch is performed to leave structures similar to sidewall spacers along the edges of the region 402. The substrate after etch is shown in FIG. 4B. After removal of the oxide 402, the single edge features 403a remain, as shown in FIG. 4C. By use of this method, the single edge features 403a may have a dimension of approximately 0.1.mu.or less. This method may be used to form, for example, a polysilicon gate of a transistor. Since the single edge feature 403a is formed along all edges of oxide region 402, it has the loop like structure described above in connection with the phase-edge layer. Therefore, deposition of a further photosensitive layer, and exposure to a second mask (such as mask 200) is performed, followed by a polysilicon etch to remove unwanted portions of spacer 403a. The patterning and etch steps may be performed either before or after removal of the oxide layer 402. This method has the same problem as described for the phase-edge method, wherein it is extremely difficult to layout the layer which forms the regions 402.
What is needed is a method for producing a layout for the phase-edge technique, or for the single edge feature technique. The method should provide a circuit designer with an efficient way to automatically produce a layout from which the phase-edge layer and feature layer may be produced. Further, methods of patterning photoresist layers using masks designed according to the layout method are needed.